Speaker:

Joel S. Emer, Professor of the Practice, MIT, Sr. Distinguished Research Scientist, Nvidia

Talk Title:

It All Depends: A Personal Perspective on the Evolution of Computer Architecture

Date and Location:

Friday, January 9, 2026

3–4 p.m.

BA 7231

There is no registration required to attend this event in person. However, seating is limited, so arriving early is recommended.

Abstract:

Over his nearly 50 year career in computer architecture research processor performance has improved by over three orders of magnitude. Those improvements have been premised on improvements at every level of a long-standing stack of abstractions. That stack is comprised of: (1) algorithms expressed in programming languages that are (2) converted by compilers into sequences of instructions that are (3) executed on computer architectures that are (4) implemented using transistors in the latest technology. In this talk, he is going focus on the computer architecture level of the stack, where execution of instructions occurs. At that level, the intrinsic nature of instructions has remained relatively constant, but the techniques to execute them quickly have evolved significantly. At its heart, however, executing instructions is a step-by-step process where each step depends on information generated at prior steps. And therefore, dealing with those dependencies is what determines the performance of the architecture. So in the first part of this talk, he will frame a number of the techniques that have been employed to optimize performance as instances of a set of methods that can mitigate the impact of dependencies between (and within) instructions. Although the abstraction stack and nature of instructions has remained remarkably constant over more than the last 50 years, that is now likely to change. That is due to the end of long-term technology scaling trends (usually referred to as Moore's Law and Denard scaling) that is limiting the ability to keep making improvements without changing stack or at least the interfaces between levels. So in the second part of the talk, he will discuss my philosophical perspective on the important attributes of the existing stack and provide some thoughts on how to both preserve those attributes and improve performance. 

Biography:

Joel S. Emer is a Professor of the Practice at MIT's Electrical Engineering and Computer Science Department (EECS) and a member of the Computer Science and Artificial Intelligence Laboratory (CSAIL). He is also a Senior Distinguished Research Scientist at Nvidia in Westford, MA, where he is responsible for exploration of future architectures as well as modeling and analysis methodologies. Prior to joining Nvidia, he worked at Intel where he was an Intel Fellow and Director of Microarchitecture Research. Previously he worked a Compaq and Digital Equipment Corporation (DEC). For nearly 50 years, Dr. Emer has held various research and advanced development positions investigating processor micro-architecture and developing performance modeling and evaluation techniques. He has made architectural contributions to a number of VAX, Alpha and X86 processors and is recognized as one of the developers of the widely employed quantitative approach to processor performance evaluation. He has also been recognized for his contributions in the advancement of deep learning accelerator design, spatial and parallel architectures, processor reliability analysis, memory dependence prediction, pipeline and cache organization, performance modeling methodologies and simultaneous multithreading. He earned a doctorate in electrical engineering from the University of Illinois in 1979. He received a bachelor's degree with highest honors in electrical engineering in 1974, and his master's degree in 1975 – both from Purdue University. Among his honors, he is a Fellow of both the ACM and IEEE, and a member of the NAE. He also received both the Eckert Mauchly award and the B. Ramakrishan Rau award for lifetime contributions in computer architecture.